Existing programmable logic devices do not provide a mechanism to maintain the autonomy of programmed functions especially when the functions are independently designed. Moreover, existing programmable logic devices do not provide dedicated bus routing resources for such programmed functions. Routing resources used for busing in existing programmable logic devices are typically uni-dimensional; namely, the routing resources are capable of conveying signals along one axis, but not along both axes. FIG. 1 illustrates exemplary prior art routing architectures in programmable logic devices. A programmable logic device 100 implemented a s a standard field programmable gate array (FPGA) includes vertical routing lines 101 and horizontal routing lines 104 interconnected to logic modules 102 via local routing lines or interconnect 103.
Current FPGA hierarchical routing relies upon segment lengths from short local routes (e.g., interconnect 103) to chip-wide long routes (e.g., vertical routing lines 101 and horizontal routing lines 104) to interconnect the various modules 102. This routing hierarchy does not allow functions of variable size to be autonomously implemented in modules 102.
Some FPGAs are equipped with chip-wide 3-state route resources which are commonly used for bussing. However, these 3-state resources are limited to bussing in one direction, either horizontally or vertically, but not both. Even in devices that contain 3-state resources in both dimensions (horizontally and vertically), such 3-state resources still do not interconnect. Moreover, these routing resources are not dedicated for busing.
Because of the undedicated nature of the conventional interconnect 101 and 104, functions implemented across several modules 102 will incur performance degradation. Furthermore, autonomous functions that have logic commingled within a module 102 will incur additional performance degradation. Performance degradation due to the commingling of disparate logic is a significant obstacle in merging autonomous functions.
In view of the foregoing, it would be highly desirable to provide a mechanism for grouping bussed resources that is capable of simultaneously interconnecting logic modules in both a conventional local/global approach and in a bussed manner between local modules. Such a technique would allow function autonomy after merging.